As semiconductor devices are required to be more highly integrated, their design rules are reduced. Accordingly, it may be more challenging to form a pattern having a small line width on an integrated circuit substrate. Moreover, efforts are being made to reduce resistance of patterned integrated circuit structures. Attempts are being made to use materials having low electrical resistance and to replace inter-wiring insulating materials with lower dielectric constant insulating materials. In particular, a low dielectric constant insulating material layer may be used for a semiconductor device whose line width is small, for example, a semiconductor device having a line width of 65 nm or less. Unfortunately, the use of low dielectric constant insulating materials may result in lower device yields if the etching rates of these materials cannot be carefully controlled.